During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes (photolithography), a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
Typically, in photolithography steps, one or more antireflective coating (ARC) layers, for example, a bottom antireflective coating (BARC) and/or a dielectric antireflective coating (DARC) layer are provided under a photoresist mask. These layers minimize or eliminate reflections during exposure of the photoresist that may produce standing waves. Such standing waves may result in defects such as sinusoidal “scalloping” of the photoresist sidewalls, or the formation of “feet” at the base of the photoresist layer. Therefore, BARC/DARC layers are generally disposed below a photoresist layer and above other device materials (e.g. SiO2) to be etched through the photoresist mask. BARC/DARC layers may be organic-based or inorganic-based, and are usually composed of different materials than the underlying dielectric material. For example, an inorganic BARC layer may be composed of titanium nitride (TiN) as well as silicon oxynitride (SiON).
The critical dimension (CD) uniformity in ultra large scale integrated circuits (ULSI) is a crucial parameter for high performance devices. The CD uniformity in the gate electrode, for example, affects the threshold voltage distribution and the overall yield of the devices. As the design rules of ULSI reduced, the roughness of the edges of the lines (Line Width Roughness: LWR) of linear features patterned by photolithography becomes worse. The LWR is a measure of how smooth the edge of a linear feature is when viewed from the top down. The ideal feature has an edge that is “straight like a ruler” as shown in FIG. 1A. However, for various reasons, the line feature may sometimes instead appear jagged as shown in FIG. 1B. Jagged lines (i.e., with a high LWR) are generally very undesirable because the CD measured along the liner feature would vary from position to position, rendering operation of the resulting device unreliable.
Argon-fluoride (ArF) excimer laser having wavelength of 193 nm (ArF lithography technology) has been used to for the production of sub 0.04 μm devices. The immersion 193 nm lithography technology enables processes below the 110 nm node. Such small features in most highly integrated circuits require higher resolution and the CD uniformity. Accordingly, the LWR problem worsens in the 193 nm lithography technology.